Nichtflüchtiger Speicher mit Gestapeltem Transistorpaar

Details

Veröffentlichungs-Nr.

EP4715819

Anmeldetag

18. September 2024

Veröffentlichung

25. März 2026

Rechtsraum

EP

IPC

G11C11/16

Abstract

A bit cell (100) is disclosed, comprising a non-non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal switching a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source/drain terminal (121) of the transistor arrangement, and a second common source/drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor arrangement comprises a stacked complementary transistor pair, wherein a gate (213) of an upper transistor is connected to a first word line (WLN) and wherein a gate (223) of a lower transistor is connected to a second word line (WLP). A memory device comprising an array of such bit cells, as well as a method for controlling a bit cell, are also disclosed.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete