Speichervorrichtung und Betrieb davon

Details

Veröffentlichungs-Nr.

EP4715823

Anmeldetag

29. April 2023

Veröffentlichung

25. März 2026

Rechtsraum

EP

IPC

G11C16/34

Abstract

In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the rows of memory cells through the word lines. Each memory cell is set to one of 2^N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit is configured to program, in a first pass, a select row of the rows of the memory cells based on N data pages, such that each memory cell of the selected row is set to one of k intermediate levels, where k is an integer not greater than 2^N. The peripheral circuit is also configured to read M data pages of the N data pages from the select row after the first pass, where M is an integer smaller than N.

Anmelder

Firma

Yangtze Memory Technologies Co., Ltd.

Land

🇨🇳 China

Fachgebiete