Prozessorarchitektur zur Parallelen Verarbeitung mehrerer Befehle

Details

Veröffentlichungs-Nr.

EP4718244

Anmeldetag

22. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

IPC

G06F9/38

Abstract

A processor comprising: a program memory for storing instructions; a decoder adapted to convert the instructions into respective operation codes and enable signals; a controller including an instruction word consisting of a plurality of instruction slots for providing the instructions to the decoder; a plurality of processing elements, each processing element being configured to operate during a time slot in accordance with an operation code provided to an input of the considered processing element so as to apply a mathematical operation to an input data element and generate an output data element, wherein an instruction provided via an instruction slot identifies one or more target processing elements to be used for executing the considered instruction, wherein the enable signals are adapted to control assignment of the operation codes to the processing elements; interconnection circuitry adapted to provide any of the operation codes to any of the processing elements at each time slot and configured to be operated in accordance with the enable signals.

Anmelder

Firma

Nokia Solutions and Networks Oy

Land

🇫🇮 Finnland