Vorrichtung und Verfahren zur Feinkörnigen Benutzermodussteuerung zum Lesen von Leistungsüberwachungszählern

Details

Veröffentlichungs-Nr.

EP4718265

Anmeldetag

16. Juli 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

IPC

G06F11/34, G06F11/30

Abstract

An apparatus for managing access to performance counters. one embodiment of a processor comprises: a plurality of cores to execute first program code at a first privilege level and second program code at a second privilege level higher than the first privilege level, a core of the plurality of cores comprising: performance monitoring circuitry including a plurality of performance counter control registers to indicate events to be counted by a corresponding plurality of performance counters; and a processor control register to store a global control value to indicate whether the first program code is permitted to read values from the corresponding plurality of performance counters; wherein each performance counter control register is to store a per-counter control value to indicate whether the first program code executed at the first privilege level is permitted to read a corresponding value from a respective performance counter, regardless of the global control value.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA