Gemeinsame Kommunikationsressource in einer Neuronalen Verarbeitungseinheit (npu) mit Multitile-In-Memory-Computing (imc)

Details

Veröffentlichungs-Nr.

EP4718271

Anmeldetag

16. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

IPC

(JUNG JIN-KYOUNG et al.)(TRAN HIEU VAN et al.)

Abstract

A first in-memory computation (IMC) circuit includes a first IMC processing tile coupled for data communication to a first interface circuit. A second IMC circuit includes a second IMC processing tile coupled for data communication to a second interface circuit. A shared resource bus connects the first and second interface circuits. The first and second interface circuits are controlled by mode control signals to operate in: a first communications mode where signal lines of the shared resource bus support data communications between the first and second IMC circuits; and a second communications mode where a first subset of signal lines of the shared resource bus support data communications between the first and second IMC circuits and a second, different, subset of signal lines of the shared resource bus are driven to a fixed voltage level to provide shielding for the data communications over the first subset of signal lines.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz