Verfahren und Vorrichtung zur Halbleiter-Chipfehleranalyse unter Verwendung mehrerer Bildgebungswerkzeuge

Details

Veröffentlichungs-Nr.

EP4718377

Anmeldetag

22. August 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Methods and apparatus for semiconductor die fault analysis are disclosed. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA