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Details

Veröffentlichungs-Nr.

EP4718456

Anmeldetag

20. August 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Embodiments herein relate to Static Random-Access Memory (SRAM) where a column of cells includes first and second sets of bit lines. First and second pre-charge circuits are also provided to allow independent precharging of the sets of bit lines such as for write or read operations. For a read operation, a sense circuit for the column is coupled to one of the sets of bit lines by a multiplexer. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. Additionally, the first and second sets of bit lines can be provided in top and bottom metal layers, respectively, of the stack. In another option, a third set of bit lines is provided using an intermediate metal layer.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA