Schaltkondensatorwandler

Details

Veröffentlichungs-Nr.

EP4718701

Anmeldetag

20. August 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

IPC

H02M3/07, H02M1/08, H02M1/00

Abstract

An apparatus includes a clock generation circuit coupled to a power train (PTR) circuit. The clock generation circuit includes an adaptive delay circuit to generate a first clock signal and a first clock delay signal based on a regulation clock signal. The clock generation circuit includes a fixed time delay circuit to generate a second clock signal and a second clock delay signal based on the regulation clock signal. The PTR circuit is to receive the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal. The PTR circuit generates a voltage output signal based on the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA