Flip-Flops mit mehreren Datenhaltewegen

Details

Veröffentlichungs-Nr.

EP4718721

Anmeldetag

10. März 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.

Anmelder

Firma

GlobalFoundries U.S. Inc.

Land

🇺🇸 USA