Strukturierte Spärliche Matrixbeschleunigung in Systolischen Arrays

Details

Veröffentlichungs-Nr.

EP4722949

Anmeldetag

2. April 2025

Veröffentlichung

8. April 2026

Rechtsraum

EP

IPC

G06F17/16

Abstract

Methods, systems, and apparatus, including computer-readable storage media for hardware-accelerated fine-grained sparse computation. The accelerator provides for improved performance for structured fine-grained sparse AI workloads, for example by accelerating sparse matrix multiplication required to execute or train AI models. Sparse data is compressed to remove zero-valued elements before being streamed into a matrix multiplication unit (MXU) of the accelerator. The accelerator stores a gains matrix, which can be the matrix for multiplying with the received input matrix. The accelerator uses an index array mapping locations of elements in the compressed matrix with locations of elements in the matrix's precompressed form, to generate a multiplier matrix from the gains matrix. Aspects of the disclosure also provide for accelerated gains matrix loading in a hardware accelerator or other type of processor. The accelerator can load the gains matrix more efficiently in a compressed form, and then un-compress the matrix once loaded.

Anmelder

Firma

Google LLC

Land

🇺🇸 USA