Dreidimensionale Integrierte Schaltung

Details

Veröffentlichungs-Nr.

EP4723112

Anmeldetag

1. Oktober 2024

Veröffentlichung

8. April 2026

Rechtsraum

EP

IPC

(LIEN YU-CHUNG et al.)

Abstract

A three-dimensional integrated circuit, comprising a first tier, a second tier, vertically stacked above the first tier, and a memory circuit. The memory circuit comprises a bitcell array disposed in the first tier. The memory circuit also comprises a column peripheral circuit having at least an elongate first portion disposed in the second tier. The memory circuit also includes a row decoder being elongate and disposed in the second tier and extending in a direction parallel to the first portion of the column peripheral circuit.

Anmelder

Firmen

Imec VZW
Katholieke Universiteit Leuven, KU Leuven R&D

Land

🇧🇪 Belgien