Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4723173

Anmeldetag

25. Dezember 2024

Veröffentlichung

18. September 2025

Rechtsraum

EP

IPC

H01L25/00, H01L23/40, H05K1/14

Abstract

To reduce the number of members needed for wiring and the number of wiring connection steps so as to improve assemblability and reduce costs. A semiconductor device includes a first circuit board (10), a second circuit board (20), and a semiconductor chip group (30). The semiconductor chip group (30) is sandwiched between the first circuit board (10) and the second circuit board (20). The first circuit board (10) includes a first insulating plate (11), a first conductive plate (12), and a second conductive plate (13). The first conductive plate (12) is embedded in the first insulating plate (11) with a first front surface (12a) and a first back surface (12b) exposed. The second conductive plate (13) is embedded in the first insulating plate (11) with a second front surface (13a) and a second back surface (13b) exposed so as to be separated from the first conductive plate (12). The second circuit board (20) includes a second insulating plate (21) on which a conductive pattern layer is laid.

Anmelder

Firma

Fuji Electric Co., Ltd.

Land

🇯🇵 Japan

Fachgebiete