Digitale Sortierung mit Niedriger Leistungsaufnahme

Details

Veröffentlichungs-Nr.

EP4726529

Anmeldetag

1. Oktober 2025

Veröffentlichung

15. April 2026

Rechtsraum

EP

IPC

G06F7/24

Abstract

The present invention concerns an electronic circuit (5) and a method of sorting data elements provided in a memory array (20), wherein the memory array (20) comprises a number of memory areas (21, 22, 23, 24), each of which configured to store a data element (11, 12, 13, 14), the method comprises the steps of:- assigning a comparison counter (31, 32, 33, 34) to each data element (11, 12, 13, 14),- comparing a first data element (11) stored in a first memory area (21) with all further data elements (12, 13, 14) stored in the number of memory areas (22, 23),- incrementing a counter value of the comparison counter (31) of the first data element (11) if the comparison of the first data element (11) with any one of the further data elements (12, 13, 14) matches a predefined comparison condition, else incrementing the comparison counter of the other data element,- concurrently or sequentially comparing further data elements (12, 13...) with all subsequent data elements (13, 14...), and incrementing each associated counter value upon the success of the comparisons, in this way the counter value of all comparison counters (31, 32, 33, 34) of the respective data elements (11, 12, 13, 14) reflects the size of each data element of the memory array (20), in which respective data elements are actually stored, and- sorting the data elements (11, 12, 13, 14) on the basis of the comparison counters (31, 32, 33, 34).

Anmelder

Firma

EM Microelectronic-Marin SA

Land

🇨🇭 Schweiz

Fachgebiete