Verfahren zur Herstellung eines Gatestapels

Details

Veröffentlichungs-Nr.

EP4726771

Anmeldetag

11. Oktober 2024

Veröffentlichung

15. April 2026

Rechtsraum

EP

Abstract

The present invention provides a method for forming a gate stack (100) on a semiconductor substrate (102), the method comprising:forming a dielectric interlayer (103) on the semiconductor substrate (102),forming a dipole-forming layer (104) comprising a work function shifting metal and oxygen on top of the dielectric interlayer (103);etching the dipole-forming layer (104) such that a residue (106) of the dipole-forming layer (104) remains on the dielectric interlayer (103), the residue (106) being less than one monolayer of the dipole-forming layer (104), wherein a temperature is kept below 430 °C between said acts of forming the dipole-forming layer (104) and etching the dipole-forming layer (104);depositing a gate dielectric (108); anddepositing a metal gate (110) on the gate dielectric (108).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien