Halbleiterchip mit Transistoren

Details

Veröffentlichungs-Nr.

EP4727292

Anmeldetag

9. Oktober 2024

Veröffentlichung

15. April 2026

Rechtsraum

EP

Abstract

A semiconductor chip comprising a plurality of first transistors and a plurality of second transistors is provided. The plurality of first transistors are configured such that they may be more robust than the second transistors against the application of high fields during turn on, such as those that may be experienced during hard switching. Specifically, the first transistors may have a larger gate to drain spacing, and/or may be designed to have additional barrier, passivation, and/or buffer layers. There is further provided control circuitry that, during turn on, controls the gate terminals of each of the first transistors to allow conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the second transistors to allow conduction between the respective drain terminals and source terminals. Furthermore, during turn off, the control circuitry controls the gate terminals of each of the second transistors to block conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the first transistors to block conduction between the respective drain terminals and source terminals. Accordingly, the first transistors and control scheme may ensure that the first and second transistors are collectively robust, whilst second transistors can be designed to suit other needs, such as a smaller footprint, smaller source-drain on resistance, lower cost and reduced complexity of the overall semiconductor chip.

Anmelder

Firma

Infineon Technologies Austria AG

Land

🇦🇹 Österreich