Verfahren zur Herstellung einer Verpackung auf Paneelebene mit Zweiseitiger Plattierung

Details

Veröffentlichungs-Nr.

EP4727328

Anmeldetag

25. September 2025

Veröffentlichung

15. April 2026

Rechtsraum

EP

IPC

H10W70/60, H10W70/00(HUANG RUI et al.)

Abstract

To form an integrated circuit package, an integrated circuit die is laterally encapsulated a by a first encapsulating body. A first plating layer, including first conductive lines and a second encapsulating body, is formed over coplanar faces of the IC die and first encapsulating body. From the opposite coplanar faces, via openings are formed extending through the first encapsulating body to the first conductive lines. A second plating layer, including second conductive lines and a third encapsulating body, is formed over the opposite coplanar faces, with the second plating layer filling the via openings and electrically connecting to the IC die.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz