System und Verfahren zur Beschleunigung der Einschaltsequenz einer Leistungssicherheitsverwaltung

Details

Veröffentlichungs-Nr.

EP4729951

Anmeldetag

15. Oktober 2024

Veröffentlichung

22. April 2026

Rechtsraum

EP

Abstract

To help reduce the amount of time before a safety power management integrated circuit (PMIC) releases a processing system from a safety state, the safety PMIC includes a first digital circuitry that first configures a voltage threshold comparator and then enables a voltage regulator to provide power to the rest of the PMIC. Additionally, concurrently with the rest of the PMIC powering on, the safety PMIC includes a second digital circuitry that is distinct from the first digital circuitry and that performs a logic built-in self-test (LBIST) for a safety logic circuitry configured to monitor the voltage threshold comparator.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA