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Details

Veröffentlichungs-Nr.

EP4730052

Anmeldetag

10. Oktober 2025

Veröffentlichung

22. April 2026

Rechtsraum

EP

IPC

G04F10/00

Abstract

An FPGA is disclosed which includes a group of TDCs, a clock generator for providing a clock in common to the group of TDCs, a tag counter configured to provide a counted value of the clock, known as a tag count, in common to the group of TDCs, and a processing unit. An arbitrary TDC comprises an input signal generation part for generating an input pulse having a rising edge that occurs at the same time as the rising edge of a start signal input to the TDC, and a delay line part into which the generated input pulse is input. The processing unit is configured to calculate a first value by multiplying the value of the tag count observed at the occurrence time of the first newly generated clock pulse of the clock after the rising edge of the start signal has occurred by the pulse period of the clock, and to calculate the occurrence time of the first start signal by subtracting, from the first value, a thermometer code output by the delay line part or a converted code obtained by converting the thermometer code at the rising edge time of the first newly generated clock pulse.

Anmelder

Firma

SDT Inc.

Land

🇰🇷 Südkorea