Puf-Basiertes Verschleierungsschema für Speicherinterne Architekturen

Details

Veröffentlichungs-Nr.

EP4730199

Anmeldetag

21. Oktober 2024

Veröffentlichung

22. April 2026

Rechtsraum

EP

IPC

(ADLER ROY L et al.)

Abstract

An in-memory computation (IMC) circuit (116) is proposed, comprising - an array comprising a matrix of memory cells (112) having a plurality of rows and columns, wherein memory cells (112) within the same column are connected through a common bit line and memory cells within the same row are connected through a common word line, wherein the memory cells (112) are configured for storing weights of a trained neural network architecture, wherein the order of the weights is pre-scrambled; - at least one decoder (126) configured for outputting a number of shifting operations to be performed by each shifting register of a plurality of shifting registers (128) using a secret key; - the plurality of shifting registers (128) configured for shifting outputs of the array according to the output of the decoder (126).

Anmelder

Firma

Robert Bosch GmbH

Land

🇩🇪 Deutschland