Gate-Treiber und Elektronische Vorrichtung damit

Details

Veröffentlichungs-Nr.

EP4730316

Anmeldetag

9. September 2025

Veröffentlichung

22. April 2026

Rechtsraum

EP

IPC

G09G3/3266

Abstract

In a gate driver including a k^th stage and a k+1^th stage, each of the k^th stage and the k+1^th stage includes a logic circuit which controls a signal of a first control node and a signal of a second control node based on an input signal, a first clock signal, and a second clock signal having a phase shifted from the first clock signal, and an output circuit which outputs a third clock signal or a low gate voltage as an output signal based on the signal of the first control node and the signal of the second control node. The third clock signal has the same phase as the first clock signal, while a line, which transmits the third clock signal, is electrically separated from a line, which transmits the first clock signal.

Anmelder

Firma

Samsung Display Co., Ltd.

Land

🇰🇷 Südkorea