Selbsttaktung in einer Neuronalen Verarbeitungseinheit (npu) mit Multitile-In-Memory-Computing (imc)

Details

Veröffentlichungs-Nr.

EP4733881

Anmeldetag

15. Oktober 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

IPC

(BHOJA SUDEEP et al.)(CHANG DONG-JIN et al.)

Abstract

An internal computation clock signal is derived from a clock signal and includes a number of pulses within each clock signal period equal to a number of in-memory computation (IMC) processing tiles of a tile cluster that are included within a stall domain of a neural processing circuit. The pulses of the internal computation clock signal are selectively gated to generate corresponding internal clock signals applied to respective IMC processing tiles of the tile cluster within the stall domain. Timing of IMC processing tile processing operations is controlled by the applied internal clock signal. Data communications output from the IMC processing tiles are time multiplexed over a shared resource bus to a shared compute circuit for processing in response to the internal computation clock signal.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz