Sram-Sicherheitsarchitektur für Hohe Integrität

Details

Veröffentlichungs-Nr.

EP4733941

Anmeldetag

15. Oktober 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

IPC

G06F11/10

Abstract

According to an embodiment, a circuit includes a memory cell array storing memory words with data bits, data check bits, and address check bits. An error correction code (ECC) logic circuit includes an address ECC generator circuit generating address check bits, a data ECC generator circuit generating data check bits, an address ECC checker circuit verifying address check bits, and a data ECC checker/correction circuit verifying and correcting data bits using data check bits. A logic circuit arranges the bits within each memory word based on a predetermined arrangement. The address check bits may be scrambled within each word, with at least one as the least or most significant bit. The address ECC may use Single Error Detection Double Error Decoding (SEDDED) and the data ECC may use Single Error Correction Double Error Detection (SECDED). The architecture provides enhanced error detection and correction capabilities for high-integrity memory applications.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete