Co-Integrierte Halbleiterstruktur und Verfahren zur Herstellung einer Co-Integrierten Halbleiterstruktur

Details

Veröffentlichungs-Nr.

EP4734700

Anmeldetag

22. Oktober 2024

Veröffentlichung

29. April 2026

Rechtsraum

EP

Abstract

A method for manufacturing a co-integrated semiconductor structure (1) from a first (100) and a second (200) layer stack, the first layer stack (100) comprising a channel layer (10) and at least one sub-stack (150) on the channel layer (10), wherein each of the at least one sub-stack (150) comprises a sacrificial layer of a first type (21), a first slender layer (31) on the sacrificial layer of the first type (21), a sacrificial layer of a second type (22) on the first slender layer (31), a second slender layer (32) on the sacrificial layer of the second type (22), a further sacrificial layer of the first type (21) on the second slender layer (32), and a further channel layer (10) on the further sacrificial layer of the first type (21), the second layer stack (200) comprising a channel layer (10) and at least one sub-stack (250) on the channel layer (10), wherein each of the at least one sub-stack (250) comprises a sacrificial layer of the first type (21) and a further channel layer (10, 11) on the sacrificial layer of the first type (21), wherein a separation (S1) between the neighboring channel layers (10) of the first layer stack (100) is larger than a separation (S2) between neighboring channel layers (10) of the second layer stack (200).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien