Festwertspeicher mit Eintransistor-Festwertspeicherzellen und Verfahren zum Schreiben von Festwertspeicherkode mit Bitleitungslastoptimierung in Festwertspeicher

Details

Veröffentlichungs-Nr.

EP4738366

Anmeldetag

29. Oktober 2025

Veröffentlichung

6. Mai 2026

Rechtsraum

EP

IPC

G11C17/12, H10B20/00

Abstract

A read-only memory, ROM, (100) includes a first ROM cell (104), a second ROM cell (106), and a third ROM cell (102). The first ROM cell (104) is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor, MOS, transistor (114). The second ROM cell (106) is configured to store a second data value of the ROM code, and includes a second MOS transistor (116), wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor (114). The third ROM cell (102) is configured to store a third data value of the ROM code, and includes a third MOS transistor (112), wherein a drain node of the third MOS transistor (112) is electrically connected to a source node of the first MOS transistor (114).

Anmelder

Firma

MEDIATEK INC.

Land

🇹🇼 Taiwan