Front-End-Of-Line-Grundplan einer Integrierten Schaltung mit durch Blockierungsunterstützte Dummy-Einfügung Eingeführten Dummien und Zugehöriges Verfahren

Details

Veröffentlichungs-Nr.

EP4742081

Anmeldetag

6. November 2025

Veröffentlichung

13. Mai 2026

Rechtsraum

EP

IPC

G06F30/392

Abstract

A front-end-of-line, FEOL, floorplan (200) of an integrated circuit includes a plurality of FEOL components (202, 204, 206, 208), a non-rectangle-shaped empty region, a first FEOL dummy (218), and a second FEOL dummy (216). The non-rectangle-shaped empty region is located between the FEOL components (202, 204, 206, 208), and includes a first empty region (212) in a first direction and a second empty region (210) in a second direction perpendicular to the first direction, where the first empty region (212) has a first end connected to the second empty region (210). The first FEOL dummy (218) is inserted in the first empty region (212). The second FEOL dummy (216) is inserted in the second empty region (210). The first FEOL dummy (218) is separated from the second FEOL dummy (216) at the first end of the first empty region (212).

Anmelder

Firma

MEDIATEK INC.

Land

🇹🇼 Taiwan