Implementierung von N:m-Sparsity in einem Beschleuniger der Digitalen Datenverarbeitung im Speicher
Anmelder: INTEL Corporation 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4745753
- Anmeldetag
- 13. Oktober 2025
- Veröffentlichung
- 20. Mai 2026
- Rechtsraum
- EP
- IPC
- G06F7/544(OVSIANNIKOV ILIA et al.)
Abstract
To support flexible N:M sparsity pattern in a DCiM macro, the DCiM macro is subdivided into multiple sub-macros according to a partitioning factor P. Each sub-macro can support 1:2 sparsity ratio. Leveraging the partitioned design, the sub-macros can be grouped together to support different N:M sparsity patterns. To determine optimal N:N sparsity pattern for each layer of a neural network, an algorithm can determine the value A of a sparsity ratio A/B is based on the number of outliers in a layer, and the value B of the sparsity ratio A/B is based on the locality measure of the outliers representing the spatial distribution of the outliers. Moreover, the optimal N:M sparsity pattern that is aligned with the determined sparsity ratio A/B can be selected based on whether to prioritize latency or accuracy, or to balance both latency and accuracy.
Anmelder
- Firma
- INTEL Corporation
- Land
- 🇺🇸 USA
US-amerikanischer Halbleiterhersteller mit Sitz in Kalifornien. Entwickelt und produziert Prozessoren, Chipsätze sowie weitere Halbleiterkomponenten für Computer, Server und eingebettete Systeme.
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