Befehlspaketschema für Vliw-Cpu-Architektur

Details

Veröffentlichungs-Nr.

EP4749437

Anmeldetag

7. Januar 2022

Veröffentlichung

27. Mai 2026

Rechtsraum

EP

IPC

G06F9/38

Abstract

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet (500) comprising multiple instructions. The decode operation includes receiving the multi-instruction packet (500) that includes first and second instructions (502, 504). The first instruction (502) includes a primary portion (508) at a fixed first location and a secondary portion (510). The second instruction (504) includes a primary portion (512) at a fixed second location between the primary portion (508) of the first instruction (502) and the secondary portion (510) of the first instruction (502). An operational code portion of the primary portion (510, 512) of each of the first and second instructions (502, 504) is accessed and decoded. An instruction packet including the primary and secondary portions (508, 510) of the first instruction (502) is created, and a second instruction (504) packet including the primary portion (512) of the second instruction (504) is created. The first and second instructions packets are dispatched to respective first and second functional units.

Anmelder

Firma

Texas Instruments Incorporated

Land

🇺🇸 USA