Rechenzyklusverwaltung eines Zufallsanalog-Digital-Wandlers für ein Analoges Speicherinternes Berechnungsverarbeitungssystem

Details

Veröffentlichungs-Nr.

EP4749623

Anmeldetag

13. November 2025

Veröffentlichung

27. Mai 2026

Rechtsraum

EP

IPC

G11C7/10, G06F21/55, G06F21/75

Abstract

Computational weight data for an in-memory computation operation is stored in a column of memory cells (14). The in-memory computation operation is executed by actuating word lines (WL) connected to the column of memory cells (14) in response to feature data of the in-memory computation operation. An analog signal generated on a bit line of the column is converted, during a converter computation cycle, a digital signal. That digital signal is processed to generate an output of the in-memory computation operation. A randomization signal is generated and applied to control application of a randomized variation to the converter computation cycle. The processing of the digital signal includes adjusting the digital signal to remove error introduced by the random variation applied to the converter computation cycle. The applied random variation affects the power waveform of the in-memory computation device making it more difficult for a power-based side channel attack to succeed.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz