Schaltung mit Doppelter Datenrate und Datenerzeugungsverfahren zur Implementierung einer Präzisen Arbeitszyklussteuerung

Details

Veröffentlichungs-Nr.

EP4749924

Anmeldetag

5. Mai 2019

Veröffentlichung

27. Mai 2026

Rechtsraum

EP

IPC

H03K19/20

Abstract

A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator, and used to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals. The four multiphase clock signals are successively out-of-phase by 90°. The multiplexer is coupled to the clock divider, and used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition of and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream.

Anmelder

Firma

Yangtze Memory Technologies Co., Ltd.

Land

🇨🇳 China

Fachgebiete