Phasenfrequenzdetektor mit Gesättigtem Ausgang

Details

Veröffentlichungs-Nr.

EP4753150

Anmeldetag

18. November 2025

Veröffentlichung

3. Juni 2026

Rechtsraum

EP

IPC

H03L7/087, H03L7/089, H03L7/18

Abstract

A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit includes a plurality of reference signals, a plurality of feedback signals, a first output signal, and a second output signal. The plurality of reference signals, including a primary reference signal having a reference triggering edge. The plurality of feedback signals, including a primary feedback signal having a feedback triggering edge. The first output signal and the second output signal indicating a phase difference between the primary reference signal and the primary feedback signal. The first output signal remains asserted after the primary feedback signal arrives, when the phase difference exceeds a max phase difference indicated by a difference between the primary reference signal and the reference signal.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz