Störimpulsunterdrückung für Fsk-Demodulation

Details

Veröffentlichungs-Nr.

EP4753218

Anmeldetag

17. November 2025

Veröffentlichung

3. Juni 2026

Rechtsraum

EP

Abstract

According to an embodiment, a glitch rejection circuit includes a first stage averaging circuit with programmable length, a second stage averaging circuit, and a hysteresis comparator. The first stage implements a recursive moving sum average using a FIFO buffer to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses programmable thresholds set based on peak signal values to generate a clean output signal. The circuit removes glitches from frequency-shift keying (FSK) demodulator input signals while maintaining signal integrity at high bitrates. The programmable parameters allow optimization based on expected glitch characteristics and system requirements.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz