Verfahren zur Llm-Erleichterten Formalen Verifikationsabdeckungsschätzung

Details

Veröffentlichungs-Nr.

EP4756664

Anmeldetag

27. November 2025

Veröffentlichung

10. Juni 2026

Rechtsraum

EP

Abstract

An apparatus for performing formal verification of a system design, comprising a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A finite state machine (FSM) is configured to verify the system design responsive to the second description of the system design in the temporal logic. A formal verification (FV) tool is configured to indicate whether the system design passes or fails, wherein the FV tool is further configured to provide a verification coverage estimation of a model implemented by the FV tool using a finite elements method (FEM) triangulation mesh.

Anmelder

Firma

RTX Corporation

Land

🇺🇸 USA