Bewahrung des Befehlscodierungsraums und Minimierung der Codegrösse für Speicheroperationen unter Verwendung von Präfixbits zur Unterscheidung von Last- und Speicheretikettprüfungen

Details

Veröffentlichungs-Nr.

EP4760493

Anmeldetag

11. November 2025

Veröffentlichung

17. Juni 2026

Rechtsraum

EP

IPC

G06F9/30

Abstract

Techniques for using prefix bits to distinguish between loads and stores are described. An embodiment includes instruction decoder and execution circuitry. The instruction decoder circuitry is to decode an extended instruction set including a first and a second instruction. The first and second instructions have a format including an opcode field and a prefix field, and both have a first opcode value, corresponding to a NOP in a non-extended instruction set, in the opcode field. In the prefix field, the first instruction has a first prefix value and the second instruction has a second prefix value in the prefix field. The execution circuitry is to perform a first one or more operations related to the first instruction and a second one or more operations related to the second instruction, the first one or more operations including a load operation and the second one or more operations including a store operation.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA