Verfahren und System zur Unterbrechung von Prozessen von einer Pcie-Vorrichtung

Details

Veröffentlichungs-Nr.

EP4760504

Anmeldetag

11. Dezember 2024

Veröffentlichung

17. Juni 2026

Rechtsraum

EP

IPC

G06F9/46, G06F9/48

Abstract

The invention concerns a method (2) for interrupting a user process (A) in a high-performance computer comprising at least one compute node comprising at least a processor (11) to execute the user process (A), at least one IOMMU (12) and at least one PCIe device (13), the method (2) comprising- allocating (21) a memory region to store a union of structures, the union of structures comprising a Posted-Interrupt Descriptor "PID" structure and a User Posted-Interrupt Descriptor "UPID" structure wherein the IOMMU uses the PID structure and the processor uses the UPID structure;- Configuring (24) the IOMMU (12) with a remapping interrupt table (IRT) comprising associating an entry of the IRT with an address of the memory region of the union of structures;- interrupting (29), by the processor (11), the user process (A) using the registered interrupt handler of the UPID structure.

Anmelder

Firmen

BULL SAS
Institut National de Recherche en Informatique et en Automatique

Land

🇫🇷 Frankreich

Fachgebiete