Systeme und Verfahren für Protokolldecodierer in einem Signalanalysesystem mit Hardware-Beschreibungssprache

Details

Veröffentlichungs-Nr.

EP4764829

Anmeldetag

19. Dezember 2025

Veröffentlichung

24. Juni 2026

Rechtsraum

EP

IPC

G06F8/51

Abstract

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and/or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

Anmelder

Firma

Altera Corporation

Land

🇺🇸 USA