Bitzelle, Speicherinterne Rechenschaltung für Mehrheitsfunktionen und Speicherinternes Rechenverfahren

Details

Veröffentlichungs-Nr.

EP4769406

Anmeldetag

24. Juni 2025

Veröffentlichung

1. Juli 2026

Rechtsraum

EP

IPC

G11C11/16, G11C13/00

Abstract

A bit cell (BC) includes: a variable resistor and a first transistor connected in series between two end nodes; and a second transistor also connected between the two end nodes. Gates of the first and second transistors are connected to first and second word lines (WLs), respectively, for a row. A circuit includes an array of BCs. In each column, BCs are connected in a stack between a sense amplifier (SA) and footer device (FD). During a read operation, FDs connect the stacks to ground. Additionally, first and second WL voltages on first and second WLs for each row are such that, for any selected row, first transistors of BCs are on and second transistors are off and, for any unselected row, first transistors of BCs are off and second transistors are on. SAs compare sense currents from the stacks to a mid-level reference current to concurrently compute majority functions.

Anmelder

Firma

GlobalFoundries U.S. Inc.

Land

🇺🇸 USA

Fachgebiete