Verbesserte Dielektrische Gate-Multischicht zur Verwendung in Gate-Induzierten Quantenpunkt-Bauelementen

Details

Veröffentlichungs-Nr.

EP4770324

Anmeldetag

27. Dezember 2024

Veröffentlichung

1. Juli 2026

Rechtsraum

EP

Abstract

A quantum dot device comprising a semiconductor region (102); a first gate dielectric layer (104) of low dielectric constant dielectric material, preferably silicon dioxide, adjacent to the semiconductor region (102); a second gate dielectric layer (106) of high dielectric constant dielectric material, preferably aluminium oxide, adjacent to the first layer of low dielectric constant dielectric material (104); and a third gate dielectric layer (108) of low dielectric constant dielectric material, preferably silicon dioxide, adjacent to the second gate dielectric layer (106); wherein a thickness of the second layer (106) is less than 80% of a combined thickness of the first layer (104), the second layer (106) and the third layer (108), and more preferably less than 50%, and the thickness of the first layer (104) is less than the thickness of the third layer (108). A gate disposed on the gate dielectric layers is configured to induce quantum dots in the semiconductor layer (102). The dielectric layer structure compensates for the unwanted fixed charges present at the interface between the semiconductor (102) and the first dielectric layer (104). The second dielectric layer may be a nanolaminate.

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Firma

Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

Land

🇳🇱 Niederlande