Programmierbarer Hochgeschwindigkeitsfrequenzteiler

Details

Veröffentlichungs-Nr.

EP4779875

Anmeldetag

13. Januar 2026

Veröffentlichung

22. Juli 2026

Rechtsraum

EP

IPC

H03K23/66

Abstract

A high-speed frequency divider (100), a method for generating an output signal (110) proportional to an input signal (106) by a frequency division factor (102), and a phase-locked loop comprising a high-speed frequency divider (100) are provided. The high-speed frequency divider (100) comprises a reduced frequency clock, an asynchronous clock divider, and clock selection circuitry. The reduced frequency clock is generated by dividing an input signal (106) by a clock reduction factor (104). The asynchronous clock divider updates an initial programmed count in synchronization with the reduced frequency clock to generate a frequency divided signal. The initial programmed count is based on the frequency division factor and the clock reduction factor (104). Clock selection circuitry selects a phase of the reduced frequency clock based on a received selection signal. The output signal (110) is based on the frequency divided signal and the selected phase of the plurality of phases.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete