Resistive Speicherbasierte Speicherinterne Berechnung für die Effiziente Implementierung von Geschalteten Rekurrenten Einheiten

Details

Veröffentlichungs-Nr.

EP4783066

Anmeldetag

22. September 2025

Veröffentlichung

29. Juli 2026

Rechtsraum

EP

Abstract

The present disclosure addresses energy overheads and latency challenges of architecture design of conventional gated recurrent unit (GRU) approaches by providing a Resistive Random-Access Memory In-Memory Computing-based gated recurrent unit (RRAM IMC-based GRU) network architecture for efficient implementation of GRUs. In the present disclosure, the RRAM IMC-based GRU network architecture is used which performs Multiply-Accumulate (MAC) operations using Ohm's law for multiplication and Kirchhoff's current law for accumulation. A plurality of GRU wight parameters are mapped as device conductance in a Resistive Random-Access Memory (RRAM) memristor array structure in a skewed arrangement. An input vector is applied as voltage pulses to wordlines of the RRAM memristor array structure corresponding to values which should be multiplied and accumulated. Outputs of the MAC operation are obtained as bitline currents, which are then sampled and converted to digital values using an Analog-to-Digital Converters for interfacing with other digital post-processing units.

Anmelder

Firma

Tata Consultancy Services Limited

Land

🇮🇳 Indien