Dual-Port-Speicher mit Ladungsteilungsabschwächung

Details

Veröffentlichungs-Nr.

EP4783168

Anmeldetag

7. Januar 2026

Veröffentlichung

29. Juli 2026

Rechtsraum

EP

IPC

G11C8/16, G11C11/419

Abstract

An example memory circuit includes a memory cell coupled to a first row line, a second row line, a first bit line, and a second bit line, the first bit line and the second bit line coupled to a first node of the memory cell, the memory cell configured to store a bit; and a controller including a first write driver coupled to the first bit line and a second write driver coupled to the second bit line, the first write driver configured to, during a first time interval, apply a first voltage to the first bit line in response to a first control signal and a first data signal, the second write driver configured, during the first time interval, to apply the first voltage to the second bit line in response to a second control signal and the first data signal.

Anmelder

Firma

Avago Technologies International Sales Pte. Limited

Land

🇸🇬 Singapur

Fachgebiete