Schaltung für Skalierbare Arrayarithmetikoperation

Details

Veröffentlichungs-Nr.

EP4787147

Anmeldetag

4. Februar 2025

Veröffentlichung

5. August 2026

Rechtsraum

EP

IPC

G06F7/544

Abstract

The present disclosure provides systems, devices, and methods for array arithmetic operations, including multiplication circuitry block including a multiplying digital to analog converter, MDAC, module comprising one or more MDACs, each of the MDACs is configured to obtain two digital inputs and provides an analog output corresponding to a multiplication result of the two digital inputs, and the MDAC module is configured to obtain a plurality of pairs of two digital inputs and provide a plurality of analog outputs corresponding to multiplication values of a plurality of pairs, a charge coupled device, CCD, module including one or more CCDs, each CCD including a parallel input row configured to obtain the analog outputs from the MDAC module, wherein the number of inputs in the parallel input row corresponds to the number of analog outputs from the MDAC module, one or more intermediary rows, wherein the CCD is configured to propagate the analog inputs along the intermediary rows of the CCD for performing an addition operation of propagated analog inputs, and a parallel terminal row configured to accumulate propagated signals from the preceding intermediary rows and provide parallel analog outputs indicative of an accumulation of the propagated signals from the preceding intermediary rows. The block also includes a common output module configured to obtain the parallel analog outputs from the parallel terminal row and perform an addition operation on the obtained parallel analog outputs and provide an output analog signal indicative of the addition calculation of all the parallel analog outputs from the parallel terminal row.

Anmelder

Firmen

Rhim, Elias Seon-Young
Heyl, Max Johann

Land

🇩🇪 Deutschland

Fachgebiete