Vorrichtung und Verfahren zum Schutz vor Informationslecks vom Bus

Details

Veröffentlichungs-Nr.

EP4787212

Anmeldetag

4. Februar 2025

Veröffentlichung

5. August 2026

Rechtsraum

EP

IPC

G06F21/79, G06F12/14

Abstract

The invention concerns a processing unit comprising on a chip:- a microprocessor for reading and/or writing in an external memory via a bus, the external memory being arranged outside the chip,- an address protection unit comprising:- a swap unit implementing an address permutation scheme for protecting information leakage from the bus,- a permutation table maintaining a mapping between real address called by the microprocessor and masked address used by the swap unit to address the external memory,- shuffle buffer containing M slots among N slots of the memory address space, M<N, and- a counter table containing one counter per slot of said N slots, the counter of a slot is incremented only when an element of said slot is written in the shuffle buffer, memory addresses are considered in bunches;- a flag unit containing a flag per bunch;- an update unit configured to trigger an update algorithm when the flag has changed to a predetermined value.

Anmelder

Firma

BULL SAS

Land

🇫🇷 Frankreich

Fachgebiete