Elektronische Umwandlungsarchitektur mit einem Kontinuierlichen Zeit-Sigma-Delta-Analog-Digital-Wandler und Kalibrierungsverfahren dafür
Anmelder: STMicroelectronics International N.V. 🇨🇭
Details
- Veröffentlichungs-Nr.
- EP4787714
- Anmeldetag
- 15. Januar 2026
- Veröffentlichung
- 5. August 2026
- Rechtsraum
- EP
Abstract
A conversion architecture (10) comprising a Continuous Time Sigma Delta Analog to Digital Converter (11) comprising a loop filter (111) followed by an analog to digital converter (112) and a feedback loop (113, 113', 116) feeding back the output (v) of said analog to digital converter (112) through an internal digital to analog converter (113; 113') to obtain (110) an error signal (e(t)) with respect to a input signal (u, s(t)), which is fed to said loop filter (111), an output digital signal (ADC<sub>out</sub>) of the analog to digital converter (112) being fed to a decimation chain of decimators (14), a local oscillator (12) feeding a clock signal (CLK<sub>ADC</sub>) to said analog to digital converter (112), and, through a frequency divider (13), to said chain of decimators (14), wherein said conversion architecture (10) further comprisesa circuit arrangement (116; 116, 24) configured to obtain a calibration tone (CT) by a divided frequency (CK3) outputted by said frequency divider (13) to said chain of decimators (14) and inject said calibration tone (CT) in said feedback loop (113', 116), in particular in the input path of said analog to digital converter (112),a calibration arrangement (22, 23) which comprisesa spurious tone estimation module (22) configured to obtain an estimation (SE) of the power of a spurious tone (2th_spur) in said output signal (v) based on a decimated signal (v<sub>1</sub>) taken in said decimation chain (14), anda calibration unit (13) receiving said estimation (SE) of the power of a spurious tone (2th _spur) and configured to send a calibration signal (DAC<sub>CAL</sub>) as function of said estimation (SE) of the power of a spurious tone to said digital to analog converter (113'), which comprises an output adjustment arrangement (115; 1131, 1132) configured to adjust an output signal (DAC'<sub>out</sub>) of said internal digital to analog converter (113) based on said a calibration signal (DAC<sub>CAL</sub>).
Anmelder
- Firma
- STMicroelectronics International N.V.
- Land
- 🇨🇭 Schweiz
Schweizer Gesellschaft des Halbleiterkonzerns STMicroelectronics, die Chips und Sensoren für Automobiltechnik, Industrie und Unterhaltungselektronik entwickelt.
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