Verriegelungssystem und Verfahren für Niedrige Softerror-Rate

Details

Veröffentlichungs-Nr.

EP4790896

Anmeldetag

7. Januar 2026

Veröffentlichung

12. August 2026

Rechtsraum

EP

Abstract

Systems for and methods of reducing soft errors can be utilized in any circuit. A circuit can include a first inverter having a first inverter input and a first inverter output, a second inverter having a second inverter input and a second inverter output, and a soft error hardening circuit. The first inverter input is coupled to the second inverter output, and the second inverter input is coupled to the first inverter output. The clock input is configured to receive a clock signal. The soft error hardening circuit is coupled to the first inverter and/or the second inverter.

Anmelder

Firma

Avago Technologies International Sales Pte. Limited

Land

🇸🇬 Singapur