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Details

Veröffentlichungs-Nr.

EP4794196

Anmeldetag

30. Januar 2026

Veröffentlichung

19. August 2026

Rechtsraum

EP

IPC

H03F3/217, H03F3/187

Abstract

A circuit, comprising: a switching circuit stage comprising first and second half bridges comprising a first, high-side DMOS transistor and a second, low-side DMOS transistor, the first half bridge (HB1) and the second half bridge (HB2) comprising respective output nodes between the high-side DMOS transistor and the low-side DMOS transistor therein, the output nodes configured for supplying an electrical load via respective filter networks between the output nodes and the load; control circuitry (60) coupled to the switching circuit stage and configured to control switching sequences of the high-side and low-side transistors in the first (HB1) and second (HB2) half bridges wherein a first pair of DMOS transistors comprising the high-side DMOS transistor in one (HB2 resp. HB1) of the half bridges (HB1, HB2) and the low-side DMOS transistor in the other of the half bridges (HB1, HB2) is switched to a non-conductive state, and a second pair of transistors comprising the high-side DMOS transistor in the other (HB1 resp. HB2) of the half bridges (HB1, HB2) and the low-side DMOS transistor (L2 resp. L1) in the one (HB2 resp. HB1) of the half bridges (HB1, HB2) is switched to a conductive state. The circuit comprises: a current flow line between the output nodes in the first half bridge (HB1) and the second half bridge (HB2), the current flow line comprising an inductance having opposed terminals coupled to a first switch and a second switch, the first switch and the second switch selectively switchable between a non-conductive state and at least one conductive state; first and second capacitances coupled with the output nodes of the first half bridge (HB1) and the second half bridge (HB2). The control circuitry (60) is configured to switch the first and second switches to the at least one conductive state at intervals in said switching sequences between switching the first pair of DMOS transistors to a non-conductive state and switching the second pair of DMOS transistors to a conductive state. The control circuitry (60) is configured to provide control signals to switch at least one of said first and second switches based on a delay among a first output signal at said first output node and a second output signal at said second output node.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete