Spannungsvergleichsschaltung, Zugehörige Integrierte Schaltung und Verfahren
Anmelder: STMicroelectronics International N.V. 🇨🇭
Details
- Veröffentlichungs-Nr.
- EP4796936
- Anmeldetag
- 6. Februar 2026
- Veröffentlichung
- 26. August 2026
- Rechtsraum
- EP
- IPC
- G01R19/165
Abstract
A voltage comparison circuit (20, 30) is disclosed. A measurement circuit (20) is configured to generate a measurement signal (V<sub>S</sub>) indicative of an input voltage (V<sub>IN</sub>), wherein the measurement circuit (20) comprises a voltage divider (RA, RB). The collectors of a first npn bipolar transistor (Q1) and a second npn bipolar transistor (Q2) are coupled to a supply voltage (VDD), and the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) are coupled to an intermediate node (A) of the voltage divider (RA, RB). A first resistance (R1) is connected between the emitter of the first npn bipolar transistor (Q1) and ground (102), and a second resistance (R2) is connected between the emitter of the second npn bipolar transistor (Q2) and the emitter of the first npn bipolar transistor (Q1). An emitter area of the second bipolar transistor (Q2) is greater than an emitter area of the first bipolar transistor (Q1).A comparison circuit (32, 34, 36, 40) is configured to generate a comparison signal (PG) as a function of a first current (I<sub>Q1</sub>) flowing through the collector of the first npn bipolar transistor (Q1) and a second current (I<sub>Q2</sub>) flowing through the collector of the second npn bipolar transistor (Q2). Specifically, in response to determining that the first current (I<sub>Q1</sub>) is greater than the second current (I<sub>Q2</sub>), the comparison circuit (32, 34, 36, 40) asserts the comparison signal (PG).According to various embodiments, the voltage comparison circuit (20, 30) comprises an n-channel FET (M0) having a drain connected to the intermediate node (A), a source connected to the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) and a gate connected to a bias voltage (V<sub>B</sub>), wherein the bias voltage (V<sub>B</sub>) corresponds to or is smaller than the supply voltage (VDD).
Anmelder
- Firma
- STMicroelectronics International N.V.
- Land
- 🇨🇭 Schweiz
Schweizer Gesellschaft des Halbleiterkonzerns STMicroelectronics, die Chips und Sensoren für Automobiltechnik, Industrie und Unterhaltungselektronik entwickelt.
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