Speicherzellenprogrammierung mit Hohem Signal-Rausch-Verhältnis für Speicherinterne Berechnung

Details

Veröffentlichungs-Nr.

EP4800691

Anmeldetag

27. Februar 2026

Veröffentlichung

2. September 2026

Rechtsraum

EP

IPC

G11C11/54, G11C13/00

Abstract

An in-memory computing system (200) includes a cross-bar array (414, 514) of memory cells (402), each having a cell transistor (702) and a memristor (502) connected in series between a select line (704) and a bit line (706). A group of programming transistors (1102), located outside the cross-bar array (514) and fewer in number than the memory cells, is selectively connected in parallel with cell transistors (702) of a common row during a write mode and isolated during a read mode. This configuration increases programming current without enlarging a footprint of the cross-bar array, enabling multi-level conductance states and improved signal-to-noise ratio for analog in-memory computing. In some embodiments, the in-memory computing system is integrated with an image sensor die for on-sensor inference.

Anmelder

Firma

OmniVision Technologies, Inc.

Land

🇺🇸 USA

Fachgebiete