Transistor mit Isoliertem Gate mit Zwei Betriebsarten und Betriebsverfahren

Details

Veröffentlichungs-Nr.

EP4801221

Anmeldetag

27. Februar 2025

Veröffentlichung

2. September 2026

Rechtsraum

EP

IPC

H10D12/00, H10D62/13

Abstract

In one embodiment, the bi-mode insulated gate transistor (1), BiGT, comprises: - a pilot region (21) and a mixed region (22) at a bottom side (20), - a first region (31) at a top side (30) opposite the bottom side (20) and atop the pilot region (21), and a second region (32) at the top side (30) and atop the mixed region (22), wherein - the first region (31) and the second region (32) are each provided with a gate electrode (41, 42), and - the gate electrodes (41) in the first region (31) and in the second region (32) are electrically addressable independent from one another.

Anmelder

Firma

Hitachi Energy Ltd

Land

🇨🇭 Schweiz

Fachgebiete