Rückseitenkontakte zur Herstellung eines Gate-Verankers

Details

Veröffentlichungs-Nr.

EP4801222

Anmeldetag

22. Dezember 2025

Veröffentlichung

2. September 2026

Rechtsraum

EP

Abstract

Techniques are provided herein to form an integrated circuit having backside conductive contacts (238/240) as part of a gate tie-down structure. Backside cavities beneath a gate structure and an adjacent source region (106b) may be formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around (108) or otherwise on a semiconductor region (104) that extends from a first source region to a second source or drain region. The substrate beneath the semiconductor device is removed and replaced with a backside dielectric material (130). Lithographic operations may be performed on the backside dielectric material along with one or more anisotropic etches to form a first cavity beneath the gate structure and a second cavity beneath the first source region. The backside conductive contacts are then formed within the backside cavities.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA