Chiplet-System mit Rekonfigurierbaren Logischen Speichermakros

Details

Veröffentlichungs-Nr.

EP4804034

Anmeldetag

10. Dezember 2025

Veröffentlichung

9. September 2026

Rechtsraum

EP

Abstract

A system comprises a compute chiplet, one or more memory chiplets, and a physical interface coupling the memory chiplets to the compute chiplet. Each memory chiplet includes a plurality of physical memory macros, each having a physical width and a physical depth, and a bus coupled to the physical memory macros. The system further comprises a memory controller configured to define one or more logical memory macros, each having a logical width and a logical depth which may be different to the physical width or physical depth of the physical memory macros. Each logical memory macro includes memory cells from one or more physical memory macros. The memory controller is configured to control access to the logical memory macros by the compute chiplet. The memory controller may translate logical memory macro addresses into physical memory macro addresses for write and read operations.

Anmelder

Firma

Chipletti Ltd

Land

🇬🇧 Großbritannien